/*
 * $QNXLicenseC:
 * Copyright 2008, QNX Software Systems. 
 * 
 * Licensed under the Apache License, Version 2.0 (the "License"). You 
 * may not reproduce, modify or distribute this software except in 
 * compliance with the License. You may obtain a copy of the License 
 * at: http://www.apache.org/licenses/LICENSE-2.0 
 * 
 * Unless required by applicable law or agreed to in writing, software 
 * distributed under the License is distributed on an "AS IS" basis, 
 * WITHOUT WARRANTIES OF ANY KIND, either express or implied.
 *
 * This file may contain contributions from others, either as 
 * contributors under the License or as licensors under other terms.  
 * Please review this entire file for other proprietary rights or license 
 * notices, as well as the QNX Development Suite License Guide at 
 * http://licensing.qnx.com/license-guide/ for other information.
 * $
 */





#include <arm/sa1100.h>
#include <arm/sa1111.h>
#include <arm/primecell.h>
#include <arm/pxa250.h>
#include <arm/hy7201.h>
#include <arm/ixp1200.h>
#include <arm/ixp2400.h>
#include <arm/ixc1100.h>
#include "ep93xx_private.h"

/*
	This source file isn't included in the startup library.
	It's only used to build the asmoff.def file.

	CPU specific definitions
*/
#include "asmoff.h"

/*
 * SA-1100 specific registers etc.
 */
VALUE(SA1100_INTR_BASE,		SA1100_INTR_BASE);
VALUE(SA1100_INTR_SIZE,		SA1100_INTR_SIZE);
VALUE(SA1100_ICIP,			SA1100_ICIP);
VALUE(SA1100_ICMR,			SA1100_ICMR);
VALUE(SA1100_TIMER_BASE,	SA1100_TIMER_BASE);
VALUE(SA1100_TIMER_SIZE,	SA1100_TIMER_SIZE);
VALUE(SA1100_OSMR0,			SA1100_OSMR0);
VALUE(SA1100_OSCR,			SA1100_OSCR);
VALUE(SA1100_OSSR,			SA1100_OSSR);
VALUE(SA1100_OSSR_M0,		SA1100_OSSR_M0);
VALUE(SA1100_OIER,			SA1100_OIER);
VALUE(SA1100_OIER_E0,		SA1100_OIER_E0);
VALUE(SA1100_GPIO_BASE,		SA1100_GPIO_BASE);
VALUE(SA1100_GPIO_SIZE,		SA1100_GPIO_SIZE);
VALUE(SA1100_GRER,			SA1100_GRER);
VALUE(SA1100_GFER,			SA1100_GFER);
VALUE(SA1100_GEDR,			SA1100_GEDR);

VALUE(SA1100_UART3_BASE,	SA1100_UART3_BASE);
VALUE(SA1100_UART1_BASE,	SA1100_UART1_BASE);
VALUE(SA1100_UART_SIZE,		SA1100_UART_SIZE);
VALUE(SA1100_UTDR,			SA1100_UTDR);
VALUE(SA1100_UTSR0,			SA1100_UTSR0);
VALUE(SA1100_UTSR0_RBB,		SA1100_UTSR0_RBB);
VALUE(SA1100_UTSR0_REB,		SA1100_UTSR0_REB);
VALUE(SA1100_UTSR1,			SA1100_UTSR1);
VALUE(SA1100_UTSR1_TNF,		SA1100_UTSR1_TNF);
VALUE(SA1100_UTSR1_RNE,		SA1100_UTSR1_RNE);
VALUE(SA1100_UTSR1_TBY,		SA1100_UTSR1_TBY);

VALUE(SA1100_RESET_BASE,	SA1100_RESET_BASE);
VALUE(SA1100_RESET_SIZE,	SA1100_RESET_SIZE);
VALUE(SA1100_RSRR,			SA1100_RSRR);
VALUE(SA1100_RSRR_SWR,		SA1100_RSRR_SWR);

/*
 * SA-1111 specific registers
 */
VALUE(SA1111_INTR,			SA1111_INTR);
VALUE(SA1111_INTR_SIZE,		SA1111_INTR_SIZE);
VALUE(SA1111_INTEN0,		SA1111_INTEN0);
VALUE(SA1111_INTEN1,		SA1111_INTEN1);
VALUE(SA1111_INTSTATCLR0,	SA1111_INTSTATCLR0);
VALUE(SA1111_INTSTATCLR1,	SA1111_INTSTATCLR1);

/*
 * PrimeCell UART specific registers etc.
 */
VALUE(PRIMECELL_UART_SIZE,		PRIMECELL_UART_SIZE);
VALUE(PRIMECELL_UART_DR,		PRIMECELL_UART_DR);
VALUE(PRIMECELL_UART_FR,		PRIMECELL_UART_FR);
VALUE(PRIMECELL_UART_FR_RXFE,	PRIMECELL_UART_FR_RXFE);
VALUE(PRIMECELL_UART_FR_TXFF,	PRIMECELL_UART_FR_TXFF);

/*
 * EP93xx specific registers etc.
 */
VALUE(EP93xx_SYSCTRL_BASE, EP93xx_SYSCTRL_BASE);
VALUE(EP93xx_SYSCTRL_SIZE, EP93xx_SYSCTRL_SIZE);
VALUE(EP93xx_SYSCTRL_DEVICECFG, EP93xx_SYSCTRL_DEVICECFG);
VALUE(EP93xx_SYSCTRL_SYSSWLOCK, EP93xx_SYSCTRL_SYSSWLOCK);

VALUE(EP93xx_INTR_BASE, EP93xx_VIC_CTRL1_BASE);
/* the registers for VIC1 and VIC2 are separated by more than EP93xx_VIC_CTRL1_SIZE 
 * and we want 1 mapping hence the EP93xx_INTR_SIZE calculation below */
VALUE(EP93xx_INTR_SIZE, (EP93xx_VIC_CTRL2_BASE - EP93xx_VIC_CTRL1_BASE) + EP93xx_VIC_CTRL2_SIZE);

VALUE(EP93xx_VIC_IRQ_STATUS, EP93xx_VIC_IRQ_STATUS);
VALUE(EP93xx_VIC_INT_ENABLE, EP93xx_VIC_INT_ENABLE);
VALUE(EP93xx_VIC_INT_CLEAR, EP93xx_VIC_INT_CLEAR);
VALUE(EP93xx_VIC_VEC_ADDR_CURR, EP93xx_VIC_VEC_ADDR_CURR);
VALUE(EP93xx_VIC_VEC_ADDR_DFLT, EP93xx_VIC_VEC_ADDR_DFLT);

VALUE(EP93xx_GPIO_CTRL_BASE, EP93xx_GPIO_CTRL_BASE);
VALUE(EP93xx_GPIO_CTRL_SIZE, EP93xx_GPIO_CTRL_SIZE);
VALUE(EP93xx_GPIO_PORTA_INT_STATUS, EP93xx_GPIO_PORTA_INT_STATUS);
VALUE(EP93xx_GPIO_PORTB_INT_STATUS, EP93xx_GPIO_PORTB_INT_STATUS);
VALUE(EP93xx_GPIO_PORTF_INT_STATUS, EP93xx_GPIO_PORTF_INT_STATUS);
VALUE(EP93xx_GPIO_PORTA_INT_ENABLE, EP93xx_GPIO_PORTA_INT_ENABLE);
VALUE(EP93xx_GPIO_PORTB_INT_ENABLE, EP93xx_GPIO_PORTB_INT_ENABLE);
VALUE(EP93xx_GPIO_PORTF_INT_ENABLE, EP93xx_GPIO_PORTF_INT_ENABLE);
VALUE(EP93xx_GPIO_PORTA_INT_CLEAR, EP93xx_GPIO_PORTA_INT_CLEAR);
VALUE(EP93xx_GPIO_PORTB_INT_CLEAR, EP93xx_GPIO_PORTB_INT_CLEAR);
VALUE(EP93xx_GPIO_PORTF_INT_CLEAR, EP93xx_GPIO_PORTF_INT_CLEAR);

/* use UART1 for debug callouts */
VALUE(EP93xx_DBGUART_SIZE, EP93xx_UART1_SIZE);	// this is the larger of the 2
VALUE(EP93xx_DBGUART_DATA, EP93xx_UART_DATA);
VALUE(EP93xx_DBGUART_FLAGS, EP93xx_UART_FLAGS);
VALUE(EP93xx_DBGUART_FLAGS_RXFE, EP93xx_UART_FLAGS_RXFE);
VALUE(EP93xx_DBGUART_FLAGS_TXFF, EP93xx_UART_FLAGS_TXFF);

/* use 32 bit TIMER3 for the QTIMER callouts */ 
VALUE(EP93xx_QTIMER_BASE, EP93xx_TIMER3_BASE); 
VALUE(EP93xx_QTIMER_SIZE, EP93xx_TIMER3_SIZE);
VALUE(EP93xx_QTIMER_LOAD, EP93xx_TIMER_LOAD);
VALUE(EP93xx_QTIMER_VALUE, EP93xx_TIMER_VALUE);
VALUE(EP93xx_QTIMER_CTRL, EP93xx_TIMER_CTRL);
VALUE(EP93xx_QTIMER_CLR, EP93xx_TIMER_CLR);

VALUE(EP93xx_TIMER_CTRL_ENABLE, EP93xx_TIMER_CTRL_ENABLE);


/*
 * PXA250 specific registers etc.
 */
VALUE(PXA250_UART_SIZE,	PRIMECELL_UART_SIZE);
VALUE(PXA250_THR,		PXA250_THR);
VALUE(PXA250_RBR,		PXA250_RBR);
VALUE(PXA250_LSR,		PXA250_LSR);
VALUE(PXA250_LSR_TDRQ,	PXA250_LSR_TDRQ);
VALUE(PXA250_LSR_DR,	PXA250_LSR_DR);
VALUE(PXA250_TIMER_BASE,	PXA250_TIMER_BASE);
VALUE(PXA250_TIMER_SIZE,	PXA250_TIMER_SIZE);
VALUE(PXA250_OSMR0,			PXA250_OSMR0);
VALUE(PXA250_OSCR,			PXA250_OSCR);
VALUE(PXA250_OSSR,			PXA250_OSSR);
VALUE(PXA250_OSSR_M0,		PXA250_OSSR_M0);
VALUE(PXA250_OIER,			PXA250_OIER);
VALUE(PXA250_OIER_E0,		PXA250_OIER_E0);
VALUE(PXA250_INTR_BASE,	PXA250_INTR_BASE);
VALUE(PXA250_INTR_SIZE,	PXA250_INTR_SIZE);
VALUE(PXA250_ICIP,		PXA250_ICIP);
VALUE(PXA250_ICMR,		PXA250_ICMR);
VALUE(PXA250_GPIO_BASE,	PXA250_GPIO_BASE);
VALUE(PXA250_GPIO_SIZE,	PXA250_GPIO_SIZE);
VALUE(PXA250_GRER0,		PXA250_GRER0);
VALUE(PXA250_GFER0,		PXA250_GFER0);
VALUE(PXA250_GEDR0,		PXA250_GEDR0);
VALUE(PXA250_GEDR1,		PXA250_GEDR1);
VALUE(PXA250_GEDR2,		PXA250_GEDR2);

/*
 * HY7201 specific registers etc.
 */
VALUE(HY7201_PMU_BASE,				HY7201_PMU_BASE);
VALUE(HY7201_PMU_SIZE,				HY7201_PMU_SIZE);
VALUE(HY7201_PMU_RESET,				HY7201_PMU_RESET);
VALUE(HY7201_PMU_RESET_WARM_RESET,	HY7201_PMU_RESET_WARM_RESET);
VALUE(HY7201_PMU_PMUMODE,			HY7201_PMU_PMUMODE);
VALUE(HY7201_PMU_PMUMODE_IDLE,		HY7201_PMU_PMUMODE_IDLE);
VALUE(HY7201_PMU_PMUMODE_RUN,		HY7201_PMU_PMUMODE_RUN);
VALUE(HY7201_TIMER_BASE,			HY7201_TIMER_BASE);
VALUE(HY7201_TIMER_BASE0,			HY7201_TIMER_BASE0);
VALUE(HY7201_TIMER_CNT0,			HY7201_TIMER_CNT0);
VALUE(HY7201_TIMER_CTL0,			HY7201_TIMER_CTL0);
VALUE(HY7201_TIMER_CTL_START,		HY7201_TIMER_CTL_START);
VALUE(HY7201_TIMER_CTL_RESET,		HY7201_TIMER_CTL_RESET);
VALUE(HY7201_TIMER_CTL_REPEAT,		HY7201_TIMER_CTL_REPEAT);
VALUE(HY7201_TIMER_TOPCTL,			HY7201_TIMER_TOPCTL);
VALUE(HY7201_TIMER_TOPCTL_T0INT,	HY7201_TIMER_TOPCTL_T0INT);
VALUE(HY7201_TIMER_STATUS,			HY7201_TIMER_STATUS);
VALUE(HY7201_INTC_BASE,				HY7201_INTC_BASE);
VALUE(HY7201_INTC_ENABLE,			HY7201_INTC_ENABLE);
VALUE(HY7201_INTC_STATUS,			HY7201_INTC_STATUS);
VALUE(HY7201_GPIO_BASE,				HY7201_GPIO_BASE);
VALUE(HY7201_GPIO_PAIS,				HY7201_GPIO_PAIS);
VALUE(HY7201_GPIO_PAIM,				HY7201_GPIO_PAIM);
VALUE(HY7201_GPIO_PAIE,				HY7201_GPIO_PAIE);
VALUE(HY7201_GPIO_PAIC,				HY7201_GPIO_PAIC);
VALUE(HY7201_GPIO_PBIS,				HY7201_GPIO_PBIS);
VALUE(HY7201_GPIO_PBIM,				HY7201_GPIO_PBIM);
VALUE(HY7201_GPIO_PBIE,				HY7201_GPIO_PBIE);
VALUE(HY7201_GPIO_PBIC,				HY7201_GPIO_PBIC);
VALUE(HY7201_GPIO_PCIS,				HY7201_GPIO_PCIS);
VALUE(HY7201_GPIO_PCIM,				HY7201_GPIO_PCIM);
VALUE(HY7201_GPIO_PCIE,				HY7201_GPIO_PCIE);
VALUE(HY7201_GPIO_PCIC,				HY7201_GPIO_PCIC);
VALUE(HY7201_GPIO_PDIS,				HY7201_GPIO_PDIS);
VALUE(HY7201_GPIO_PDIM,				HY7201_GPIO_PDIM);
VALUE(HY7201_GPIO_PDIE,				HY7201_GPIO_PDIE);
VALUE(HY7201_GPIO_PDIC,				HY7201_GPIO_PCIC);

/*
 * IXP1200 specific registers etc.
 */
VALUE(IXP1200_UART_BASE,			IXP1200_UART_BASE);
VALUE(IXP1200_UART_SIZE,			IXP1200_UART_SIZE);
VALUE(IXP1200_UART_SR,				IXP1200_UART_SR);
VALUE(IXP1200_UART_SR_RXR,			IXP1200_UART_SR_RXR);
VALUE(IXP1200_UART_SR_TXR,			IXP1200_UART_SR_TXR);
VALUE(IXP1200_UART_DR,				IXP1200_UART_DR);
VALUE(IXP1200_UART_CR,				IXP1200_UART_CR);
VALUE(IXP1200_UART_CR_RIE,			IXP1200_UART_CR_RIE);
VALUE(IXP1200_UART_CR_XIE,			IXP1200_UART_CR_XIE);
VALUE(IXP1200_TIMER_BASE,			IXP1200_TIMER_BASE);
VALUE(IXP1200_TIMER_SIZE,			IXP1200_TIMER_SIZE);
VALUE(IXP1200_TIMER_1_LOAD,			IXP1200_TIMER_1_LOAD);
VALUE(IXP1200_TIMER_1_VALUE,		IXP1200_TIMER_1_VALUE);
VALUE(IXP1200_TIMER_1_CLEAR,		IXP1200_TIMER_1_CLEAR);
VALUE(IXP1200_TIMER_1_CONTROL,		IXP1200_TIMER_1_CONTROL);
VALUE(IXP1200_TIMER_CONTROL_PERIODIC,	IXP1200_TIMER_CONTROL_PERIODIC);
VALUE(IXP1200_IRQ_BASE,				IXP1200_IRQ_BASE);
VALUE(IXP1200_IRQ_SIZE,				IXP1200_IRQ_SIZE);
VALUE(IXP1200_PCI_CFG_BASE,			IXP1200_PCI_CFG_BASE);
VALUE(IXP1200_PCI_CFG_SIZE,			IXP1200_PCI_CFG_SIZE);
VALUE(IXP1200_IRQ_STATUS,			IXP1200_IRQ_STATUS);
VALUE(IXP1200_IRQ_ENABLE_SET,		IXP1200_IRQ_ENABLE_SET);
VALUE(IXP1200_IRQ_ENABLE_CLEAR,		IXP1200_IRQ_ENABLE_CLEAR);
VALUE(IXP1200_FBI_BASE,				IXP1200_FBI_BASE);
VALUE(IXP1200_FBI_SIZE,				IXP1200_FBI_SIZE);
VALUE(IXP1200_IREG,					IXP1200_IREG);
VALUE(IXP1200_IREG_CINTIRQ,			IXP1200_IREG_CINTIRQ);
VALUE(IXP1200_IREG_UEIRQ,			IXP1200_IREG_UEIRQ);
VALUE(IXP1200_IXP1200_RESET,		IXP1200_IXP1200_RESET);

/*
 * IXP2400 specific registers etc.
 */
VALUE(IXP2400_UART_BASE,			IXP2400_UART_BASE);
VALUE(IXP2400_UART_SIZE,			IXP2400_UART_SIZE);
VALUE(IXP2400_TIMER_BASE,			IXP2400_TIMER_BASE);
VALUE(IXP2400_TIMER_SIZE,			IXP2400_TIMER_SIZE);
VALUE(IXP2400_TIMER1_LOAD,			IXP2400_TIMER1_LOAD);
VALUE(IXP2400_TIMER1_STATUS,		IXP2400_TIMER1_STATUS);
VALUE(IXP2400_TIMER1_CLEAR,			IXP2400_TIMER1_CLEAR);
VALUE(IXP2400_TIMER1_CONTROL,		IXP2400_TIMER1_CONTROL);
VALUE(IXP2400_TIMER_CONTROL_ACT,	IXP2400_TIMER_CONTROL_ACT);
VALUE(IXP2400_IRQ_BASE,				IXP2400_IRQ_BASE);
VALUE(IXP2400_IRQ_SIZE,				IXP2400_IRQ_SIZE);
VALUE(IXP2400_GCAP_BASE,			IXP2400_GCAP_BASE);
VALUE(IXP2400_GCAP_SIZE,			IXP2400_GCAP_SIZE);
VALUE(IXP2400_GCAP_RESET0,			IXP2400_GCAP_RESET0);
VALUE(IXP2400_GCAP_RESET0_RSTALL,	IXP2400_GCAP_RESET0_RSTALL);

VALUE(IXP2400_IRQ_STATUS,			IXP2400_IRQ_STATUS);
VALUE(IXP2400_IRQ_ENABLE_SET,		IXP2400_IRQ_ENABLE_SET);
VALUE(IXP2400_IRQ_ENABLE,			IXP2400_IRQ_ENABLE);
VALUE(IXP2400_IRQ_ENABLE_CLR,		IXP2400_IRQ_ENABLE_CLR);

VALUE(IXP2400_PCI_CSR_BASE,			IXP2400_PCI_CSR_BASE);
VALUE(IXP2400_PCI_CSR_SIZE,			IXP2400_PCI_CSR_SIZE);
VALUE(IXP2400_XSCALE_INT_STATUS,	IXP2400_XSCALE_INT_STATUS);
VALUE(IXP2400_XSCALE_INT_ENABLE,	IXP2400_XSCALE_INT_ENABLE);


/*
 * IXP425 (IXC1100) specific registers etc.
 */


VALUE(IXP425_TIMER_BASE,	IXP425_TIMER_BASE);
VALUE(IXP425_TIMER_SIZE,	IXP425_TIMER_SIZE);
VALUE(IXP425_TIMER_STATUS_OST_BITS, IXP425_TIMER_STATUS_OST_BITS);
VALUE(IXP425_TIMER_STATUS_OST_TIMER0, IXP425_TIMER_STATUS_OST_TIMER0);
VALUE(IXP425_TIMER_STATUS, IXP425_TIMER_STATUS);
VALUE(IXP425_TIMER0_RELOAD, IXP425_TIMER0_RELOAD);
VALUE(IXP425_TIMER0_RELOAD_EN, IXP425_TIMER0_RELOAD_EN);
VALUE(IXP425_TIMER0_VAL, IXP425_TIMER0_VAL);

VALUE(IXP425_IRQ_SIZE,		IXP425_IRQ_SIZE);
VALUE(IXP425_IRQ_BASE,		IXP425_IRQ_BASE);
VALUE(IXP425_IRQ_ENABLE,	IXP425_IRQ_ENABLE);
VALUE(IXP425_IRQ_STATUS,	IXP425_IRQ_STATUS);
VALUE(IXP425_IRQ_HIPRIO,	IXP425_IRQ_HIPRIO);
VALUE(IXP425_IRQ_GPIO8,		IXP425_IRQ_GPIO8);
VALUE(IXP425_IRQ_GPIO11,	IXP425_IRQ_GPIO11);

VALUE(IXP425_IRQ_ENABLE,	IXP425_IRQ_ENABLE);
VALUE(IXP425_IRQ_STATUS,	IXP425_IRQ_STATUS);
VALUE(IXP425_IRQ_HIPRIO,	IXP425_IRQ_HIPRIO);

VALUE(IXP425_GPIO_SIZE,		IXP425_GPIO_SIZE);
VALUE(IXP425_GPIO_BASE,		IXP425_GPIO_BASE);
VALUE(IXP425_GPIO_GPISR,	IXP425_GPIO_GPISR);

/*
 * IXP465 (IXC1100) specific registers etc.
 */
VALUE(IXP465_IRQ_SIZE,		IXP465_IRQ_SIZE);
VALUE(IXP465_IRQ_ENABLE2,	IXP465_IRQ_ENABLE2);
VALUE(IXP465_IRQ_STATUS2,	IXP465_IRQ_STATUS2);


__SRCVERSION( "$URL: http://svn/product/tags/public/bsp/nto650/ATMEL-AT91SAM9G45-EKES-650/latest/src/hardware/startup/lib/arm/asmoff.c $ $Rev: 657836 $" );
